1. Field of the Invention
The invention relates to a semiconductor device and fabrication thereof, and more particularly relates to a phase change memory device and fabrication thereof.
2. Description of the Related Art
Phase change memory cell has many advantages, such as fast speed, lower power consumption, high capacity, robust endurance, easy embeddability in logic IC, and lower cost, so that it can serve as stand-alone or embedded memory devices with high integrity. Due to the described advantages, phase change memory has been considered the most promising candidate for the next-generation nonvolatile semiconductor memory which can replace the commercialized volatile memory, such as SRAM or DRAM, and non-volatile memory, such as flash.
The binary state switching in a phase change memory cell is accomplished by a fast and reversible phase transition between amorphous phase and crystalline phase in an active region of chalcogenide material, usually Ge2Sb2Te5 (GST). The switching, which is induced by pulsed Joule heating, results in either a highly resistive RESET state or a low-resistance SET state, depending on if the phase is amorphous or crystalline, respectively.
Current pulses with different durations and amplitudes may be used to program the phase change memory cell. For example, the RESET current pulse with higher amplitude and shorter width, such as 0.6 mA with 50 ns, is applied to melt the GST alloy and the melted GST alloy is then rapidly quenched to be frozen to form the disordered structure (RESET state). The RESET state of the phase change memory cell has a higher resistance ranging from 105 to 107 ohm and the phase change memory cell presents a higher voltage when a current is applied for reading. On the other hand, the SET current pulse has lower amplitude and longer time (for example, 0.3 mA and 100 ns) so as to effectively crystallize the disordered GST alloy with sufficient time. Due to low-resistance SET state ranging from 102 to 104 ohm, the phase change memory cell presents a lower voltage when a current is applied for reading. The programming of phase change memory cell is according to the above described method.
In recent years, the size and cell spacing of the phase change memory cell have been continuously shrunk with the development of phase change memory technology. FIG. 1 shows a plane view of a phase change memory array. As shown in FIG. 1, the size of the unit cell 102 determines the density of the phase change memory. If the size of the unit cell 102 can be shrunk to 5.8 F2. the distance d between neighboring cells 102 is reduced to only 2.4 F. The short neighboring distance may cause issues related to programming disturbs or thermal crosstalk between the phase change memory cells 102. The state of the phase change memory cell 102 may be affected due to the programming disturbs of neighboring memory cells.